1. Field of the Invention
The present invention relates in general to a system for uniquely identifying an integrated circuit (IC), and in particular to a device that may be embedded in the IC which, due to randomly occurring chip-to-chip or device-to-device parametric variations, produces a unique output identification for each IC chip in which it is implemented.
2. Description of Related Art
Integrated circuits are manufactured with batch processing intended to make all integrated circuit chips identical, thereby lowering manufacturing costs and improving quality. However, it is useful to be able to distinguish each individual integrated circuit from all others, for example to track its source of manufacture, or to identify a system employing the integrated circuit. Individually identifiable integrated circuits can be used to validate transactions, route messages, track items through customs, verify royalty counts, recover stolen goods, validate software, and many other uses.
It has been known to include circuits within a chip that produce a signal identifying the nature or type of the chip. U.S. Pat. No. 5,051,374, issued Sep. 24, 1991 to Kagawa et al., “Method of manufacturing a semiconductor device with identification pattern”, shows a technique for identifying the type of mask-programmed read-only memory (ROM). ROMs of different types may have indistinguishable visible structures, but the special processing steps described in this patent produce a visible pattern on the ROM identifying its nature. U.S. Pat. No. 4,150,331 issued Apr. 17, 1979 to Lacher, “Signature encoding for integrated circuits”, describes an embedded system that puts a type-specific identifier on the pins of a circuit when stimulated. U.S. Pat. No. 5,079,725 issued Jan. 7, 1992 to Geer et al., “Chip Identification Method for use with Scan Design Systems and Scan Testing Techniques”, describes a method for incorporating type specific identification into a scan test chain. These methods of identification are useful for indicating the type of component being manufactured or placed in an assembly, but they do not distinguish individual chip one from another.
It has been also known to customize each individual chip as it is manufactured in order to make it uniquely identifiable. Such customization may be performed as the chip is fabricated, typically by inscribing pattern on its die, or after it is fabricated, for example, by employing electrical or laser signals to alter its circuitry in some way. U.S. Pat. No. 5,642,307 issued Jun. 24, 1997 to Jernigan, “Die Identifier and Die Identification Method” includes a non-volatile, programmable read-only memory (PROM) on a chip. After the chip is fabricated, the PROM is programmed to store a date, a lot number, a wafer number, and a wafer position, as well as other useful manufacturing data. U.S. Pat. No. 4,419,747, issued Dec. 6, 1983, to Jordan, “Method and Device for Providing Process and Test Information in Semiconductors”, stores similar information in an extension of an existing programmable memory array. The information may be read back when an unusual combination of voltages is placed on the input pins and detected by the chip, overriding the normal function of the device.
U.S. Pat. No. 5,056,061, issued Oct. 8, 1991 to Akylas et al., “Circuit for encoding identification information on circuit die using FET capacitors” discloses the use of high voltage signals to break a capacitor structure within each individual chip so that some aspect of the chip's behavior is permanently altered in some identifiable way. U.S. Pat. No. 5,553,022, issued Sep. 3, 1996 to Weng et al., “Integrated circuit identification apparatus and method”, performs a similar breakdown on the gate oxide of a MOSFET. In both cases an oxide is permanently altered, and this requires careful circuit design and process characterization to do reliably. U.S. Pat. No. 4,766,516, issued Aug. 23, 1988 to Ozdemir et al., “Method and apparatus for securing integrated circuits from unauthorized copying and use”, teaches us to electronically after a semiconductor die with lasers or focused ion beams. While such approaches are effective to provide each chip with an ID, the additional processing steps needed to customize each individual chip add time and cost to the chip manufacturing process.
Other techniques do not result in an electrically detectable modification of the integrated circuit die. Instead, they physically inscribe a pattern onto an unused portion of the die surface, to be observed optically by a machine or by a person using a microscope. U.S. Pat. No. 5,350,715, issued Sep. 27, 1994 to Lee, “Chip identification scheme” teaches applying a pattern of dots to electrically inactive areas on each die site on a wafer. This may be done with an additional mask step applied to the whole wafer. U.S. Pat. No. 4,510,673, issued Apr. 16, 1995 to Shils et al., “Laser written chip identification method”, describes using an X-Y controllable laser beam to produce identification patterns on the surface of a chip.
While such methods can provide each chip with a unique identification, they require special processing steps during the semiconductor manufacturing process that add cost and time to the manufacturing process. What is needed is a method for reliably and easily identifying and authenticating individual integrated circuits that does not require any additional manufacturing steps or equipment.